The ROM cartridge design makes it simple to produce compatible cartridges. These are however limited to 16K in size due to the lack of a bank paging mechanism within the ZX Interface 2, and as a consequence it prohibits access to the 8K Shadow ROM within the ZX Interface 1. It is also not possible to create a mixed ROM/RAM cartridge due to the lack of decoding of the read and write memory control signals. These drawbacks place severe limitations on what applications can be implemented as ROM cartridges.

It is however possible to overcome many of the limitations of the ZX Interface 2 design using novel design techniques. A range of approaches for creating compatible ROM cartridges are described below:

To demonstrate these techniques I have created three ROM cartridge printed circuit boards (PCB), the ZXC1, ZXC2 and ZXC3. The ZXC1 PCB implements support for the standard, switched paging and timed paging cartridge configurations. The ZXC2 PCB implements support for the standard, switched paging and software paging cartridge configurations. The ZXC3 PCB implements support for the standard and software paging cartridge configurations, and adds the ability to program a FLASH ROM without the need for an EPROM programmer. I've also produced a number of new ROM cartridges that work with these PCBs.


Standard 16K ROM Cartridges

The diagram below shows how a standard 27C128 16K x 8 EPROM can be connected to form a ZX Interface 2 ROM cartridge.

27C128 EPROM Based ROM Cartridge

The 74LS32 OR gate is required because pin 27 is not used to enable the IC as is the case on an actual ROM IC. Only when both A14 and A15 are low will the /CE line of the 27C128 EPROM go low and hence the IC enabled. All unused gates on the 74LS32 should have their inputs connected to 0V. A 74HC32 can be used instead of the 74LS32 when the cartridge is used with a 16K/48K Spectrum or a Spectrum+2, but a 74LS32 must be used if the cartridge is intended to work with a Spectrum 128 as otherwise address line A14 becomes too heavily loaded.


Switched Bank Paging ROM Cartridges

An extension of the standard 16K ROM cartridge design is to use switches to select a specific bank of 16K from a larger capacity EPROM. This still imposes all of the limitations of the ZX Interface 2 design but does allow a single cartridge to contain multiple programs, though only one can be run at a time. The diagram below shows how a standard 27C256 32K x 8 EPROM can be connected to form a switched two bank ZX Interface 2 ROM cartridge.

Switched 27C256 EPROM Based ROM Cartridge

Timed Bank Paging ROM Cartridges

It is possible to overcome the 16K limitation of standard ROM cartridges by paging different banks of 16K into the memory map after specific time intervals have elapsed. As each bank is paged in, its contents must be transferred to RAM before the next bank is paged in. Once all banks have had their contents transferred to RAM, the program now assembled in RAM can be executed. A simple RC circuit can be used to toggle address line A14 of a 32K EPROM to switch between the two banks of 16K after a specific time. Two such circuits could be used with a 64K EPROM to toggle address lines A14 and A15 thus allowing access to three of the four 16K banks (potentially enough for a 48K program). The technique requires the ROM bank paged in at power up to copy a small routine to RAM and then execute it. This routine must transfer the data content of the ROM bank into RAM, and then wait for the paging of the next ROM bank to occur. When this happens, the routine must repeat the transfer cycle for all remaining ROM banks. When the data from all ROM banks has been transferred to RAM, the routine can then execute the program that now resides in RAM. Since the final ROM bank is left paged in, this approach has the drawback that the program transferred to RAM must not require access to the Spectrum's ROM.

This technique was initially demonstrated using a 32K EPROM to create a ROM cartridge of the Ultimate Play The Game title KnightLore, and details on it can be found by following the link Los Trastos de Droy on web site www.speccy.org/trastero. Note that this site is written in Spanish.

The timed bank paging design can be enhanced to completely page out the ROM cartridge from the memory map after a specific time interval has elapsed and then to re-enable the Spectrum's ROM instead. The program transferred to RAM will then have access to the Spectrum's ROM routines and this means that almost any program can be converted into ROM cartridge format. Also, once the ROM cartridge has been paged out, access to the ZX Interface 1 facilities becomes possible since its 8K Shadow ROM can now be paged in and out as required.

The diagram below shows how a standard 27C512 64K x 8 EPROM can be connected to form a 48K ZX Interface 2 ROM cartridge. To produce a 32K ROM cartridge, a 27C256 32K x 8 EPROM can be used instead of the 27C512 and the RC circuit to control address line A15 omitted. Links L1 and L2 are used to produce a 64K ROM cartridge. In this mode all four 16K banks of a 27C512 EPROM are used, but it is not possible to page the Spectrum's ROM back into the memory map.

Time Banked 27C512 EPROM Based ROM Cartridge

The values of components R1, R2, R3, R4, R5, R6, C1, C2 and C3 define the time it takes to page between the banks of 16K. The table below shows suitable values for the different ROM cartridge configurations. Bank paging occurs at approximately 0.7 second intervals. Note that the table assumes the use of a 27C512 EPROM. If a 27C128 EPROM is used instead then +5V must be presented on Vpp (pin 1) and /PGM (pin 27). If a 27C256 EPROM is used instead then +5V must be presented on /PGM (pin 27).

Cartridge TypeBank OrderL1L2R1R2C1R3R4C2R5R6C3
16K1st1-21-2OmitShortOmitShortOmitOmitOmitShortOmit
16K + Page Out1st1-21-2OmitShortOmit330k33k100uOmitShortOmit
32K1st, 2nd1-21-2OmitShortOmitShortOmitOmit22k220k100u
32K + Page Out1st, 2nd1-21-2OmitShortOmit470k47k100u22k220k100u
48K1st, 2nd, 4th1-21-233k330k100uShortOmitOmit22k220k100u
48K + Page Out1st, 2nd, 4th1-21-233k330k100u560k56k100u22k220k100u
64K2nd, 1st, 3rd, 4th2-32-333k330k100u220k22k100u47k470k100u

The cartridge types that specify 'Page Out' will end by paging the Spectrum's ROM back into the memory map.

An example software routine to coordinate the transfer of the program from the ROM banks to RAM is as follows:

         LD A,marker
         LD HL,$0000
  WAIT1: LD B,H
  WAIT2: CP (HL)
         JR NZ,WAIT1
         DJNZ WAIT2

The routine continually monitors the byte at 0000h, looking for a change in the value. Such a change indicates that the timing circuitry has switched banks. For this technique to work, the corresponding byte in both banks must have different values, and it is best to avoid value FFh since this would be returned during the period when neither bank is enabled. The routine checks that the value of the byte remains stable for 256 consecutive reads to ensure that the switch to the new bank has stabilised.


Software Bank Paging ROM Cartridges

Whilst the timed bank paging approach overcomes the 16K limitation of standard ROM cartridges, it still imposes a number of drawbacks:

These issues can be overcome using a memory mapped I/O approach, which allows banks to be switched between via software control.

To achieve this, additional circuitry on the ROM cartridge must detect whenever a range of memory locations is accessed and must page in a particular bank associated with the memory location that was accessed. It does not matter whether the memory access was a read or a write since the ZX Interface 2 design assumes that a ROM cartridge can only ever be read from due to the fact that it is a ROM. As a result, the design does not decode the read and write control lines from the CPU, and so reading or writing to a ROM location will both be treated by the ROM cartridge as a read request. The Z80 CPU contains built in dynamic memory refresh circuitry and this causes regular memory accesses to occur. The /RFSH control signal from the CPU is used to distinguish these memory accesses from reads and writes, but this signal is also not present at the ROM cartridge socket since a ROM would have no need for this signal. Therefore memory refresh operations are also treated by the ROM cartridge as read requests. To reliably use a memory mapped I/O mechansim for bank paging requires the ability to filter out all memory refresh operations so as to avoid inadvertent bank paging occurring. Note that it is not necessary to explicitly filter out memory writes since it is reasonable to assume these will never occur to a ROM device.

When a memory refresh operation occurs, the location accessed is determined by the combination of the I and R registers. The I register specifies the high order byte of the address and the R register specifies the low order byte. The first seven bits of the R register are automatically incremented by the CPU after each machine code instruction is executed, whereas the I register is set exclusively under program control. To ensure reliable memory mapped I/O operation, the value of the I register must be set so that the combination IR cannot inadvertently invoke the bank paging mechanism no matter what value the R register holds. Since any memory mapped addresses can no longer be used to hold program code or data, it is convenient to locate these addresses at one end of the ROM area, thereby ensuring the largest possible contiguous range of addresses for a ROM program. At power up, the I and R registers default to values of 0 and so if the memory mapped I/O were located that the bottom range of addresses then the mechanism would be immediately invoked. It is therefore preferrable to locate the memory mapped I/O at the top of the ROM area. The I register must then not be set such that the memory refresh cycle overlaps with the memory mapped I/O address range.

The diagram shown below uses the 64 memory locations at the top of the ROM area (addresses 3FC0h - 3FFFh) to operate the bank paging mechanism. To ensure reliable operation, the I register must never hold the value 3Fh.

Software Banked EPROM Based ROM Cartridge

To individually access each location within the 64 byte memory mapped range requires 6 address lines, A0 - A5. The purpose of each memory mapped location is as follows:

ZXC2 PCB Memory Mapped Control

The first four bits are used to select one of 16 possible banks of 16K, the exact number being determined by the capacity of EPROM used. The fifth bit is used to page the ROM cartridge in and out of the memory map. When paged out of the memory map, the spectrum's ROM is re-enabled and hence its routines can be utilised. In this state, it is also possible to access the Shadow ROM of the ZX Interface 1 and therefore the facilities it provides. The sixth bit is used to lock the currently select ROM bank settings thereby preventing further bank paging from occurring. This is useful in the situations where the full 16K ROM space is required for a program.

An example software routine to switch between ROM banks is as follows:

         .
         .
         LD A,($3FC1)
         .              ;Next instruction runs from bank 1
         .
         .
         LD A,($3FC0)
         .              ;Next instruction runs from bank 0
         .


Programmable Software Bank Paging ROM Cartridges

This technique extends upon the Software Bank Paging mechanism by adding the ability to program a FLASH ROM directly from the Spectrum. The design uses a 29F010 FLASH ROM, which requires a /WE line to instruct the ROM that a write is required. However, the ROM cartridge connector provided by the ZX Interface 2 does not expose /RD and /WR lines since its design assumes that a read-only ROM will be installed within a cartridge and hence any access to must be a read. It is therefore necessary for the enhanced ROM cartridge to create its own read and write control lines.

To achieve this, one of the D-type flip-flops of the software bank page design that was used in the selection of the active RAM bank is instead used as a write line. As a result, the maximum capacity FLASH ROM supported is 128K. When the flip-flop outputs a logic 1, write mode is selected. When the flip-flop outputs a logic 0, read mode is selected. At power on, read mode is selected and hence the ROM cartridge operates just like an EPROM based cartridge. To program a byte within the FLASH ROM, it is necessary to activate write mode, performing one or more write operations, and then deactive write mode. The 29F010 FLASH ROM incorporates a command interface which requires a special sequence of accesses in order to program a byte. The sequence required is as follows:

This can be implemented as follows:

  ;Send command code 'Unlock 1' - Write $11555,$AA

         LD A,($3FC9)   ;Select bank 1 and write mode.
         LD A,$AA
         LD ($1555),A   ;Write 'Unlock Code 1' command.

  ;Send command code 'Unlock 2' - Write $02AAA,$55

         LD A,($3FC8)   ;Select bank 0 and write mode.
         LD A,$55
         LD ($2AAA),A   ;Write 'Unlock Code 2' command.

  ;Send command code 'Program' - Write $11555,$A0

         LD A,($3FC9)   ;Select bank 1 and write mode.
         LD A,$A0
         LD ($1555),A   ;Write the 'Program' command.

  ;Write the byte to the address within the bank

         LD A,($3FC8+n) ;Select bank n and write mode.
         LD A,$yy
         LD ($xxxx),A   ;Write byte yy to address xxxx.

  ;Select read mode

         LD A,($3FC0+n) ;Select bank n and read mode.

Programming a byte is not instantaneous but instead takes a relatively long period of time. The 29F010 ROM command interface therefore allows the status of the operation to be checked to determine when it has completed and whether it was successful. The command interface also supports other sequences that allow individual banks to be erased, and even the entire ROM to be erased in one operation. For full details on these sequences, refer to the datasheet for the 29F010 FLASH ROM.

Click here to download the 29F010 FLASH ROM datasheet.

The diagram shown below uses the 64 memory locations at the top of the ROM area (addresses 3FC0h - 3FFFh) to operate the bank paging mechanism and the FLASH programming mechanism. As a result, it is only possible to program addresses 0000h - 3FBFh. To avoid the potential for unintentionally activating the paging circuitry, the I register should never hold a value of 3Fh. Since there must never be any extraneous memory accesses whilst programming the FLASH ROM, the I register must never hold a value below 40h. To avoid 'snow'/crashes due to memory contention with the ULA, the safe range of values to set the I register to is 80h to BFh.

Software Banked EPROM Based ROM Cartridge

The circuit introduces another new feature over to the Software Bank Paging mechanism, which is that it can automatically detect when the Spectrum has been reset and can therefore reset the bank paging mechanism in response. This is achieved by monitoring the /MREQ line, which will be continuously pulsing if the Spectrum is running. The /MREQ line is activated whenever the CPU executes an instruction from ROM or RAM. Even if the CPU is stopped via a HALT instruction, the automatic RAM refresh circuitry built into the Z80 will perform periodic activation of the /MREQ line. It is only when the reset button of the Spectrum+/128/+2 is pressed that the CPU is completely stopped and the /MREQ line becomes idle. The /MREQ line is normally at logic 1 (5V) and pulses to logic 0 (0V) when a memory access occurs. This signal is inverted and applied via a diode to a capacitor. The diode and capacitor form a sample-and-hold circuit and will hold 5V whilst regular memory accesses occur. This output of the peak detector is feed into the reset input of the bank paging flip-flops. When the Spectrum+/128/+2 reset button is pressed, the capacitor is no longer topped up and begins to discharge. Eventually it will discharge enough to cause a reset of the flip-flops. Note that when operating Microdrives, the Interface 1 ULA can active the /WAIT control line of the Z80, thereby suspending it. When suspended, no activity appears on the /MREQ line and so the voltage held by the sample-and-old circuit begins to decay. Since these CPU suspension periods can last for several milliseconds, the discharge rate of the sample-and-hold circuit is chosen so that it is does not falsely trigger a reset of the flip-flops.

To individually access each location within the 64 byte memory mapped range requires 6 address lines, A0 - A5. The purpose of each memory mapped location is as follows:

ZXC3 PCB Memory Mapped Control

The first three bits are used to select one of 8 possible banks of 16K. The fourth bit is used as a read/write control line. The fifth bit is used to page the ROM cartridge in and out of the memory map. When paged out of the memory map, the spectrum's ROM is re-enabled and hence its routines can be utilised. In this state, it is also possible to access the Shadow ROM of the ZX Interface 1 and therefore the facilities it provides. The sixth bit is used to lock the currently select ROM bank settings thereby preventing further bank paging from occurring. This is useful in the situations where the full 16K ROM space is required for a program.


Some alternate ROM cartridge designs have been produced by others, and can be viewed by following the links below. Note that these websites are not written in English.